The Design of a Real–Time Image Manipulation Chip Set

This paper discusses the design of a real–time image processing system, realized by student design teams. The system requirements are to rotate, scale and translate digitized images of a 1024 times 1024 size at a rate of 25 images per second. Today’s standard image processors can not satisfy these constraints so other solutions have to be considered. The system we propose is a system build with two different ASICs. The first ASIC is a so called affine transformer which generates a coordinate pair. The second ASIC is a bilinear interpolator which calculates an intermediate pixel value out of the four surrounding pixel values. Using two transformers and one interpolator, one can build up a system which can translate, rotate and scale an image of a size of 1024 times 1024 pixels in real–time with a satisfying image quality. The final design of this system was made by a design team consisting of students.